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ADM1041
MICROPROCESSOR SUPPORT
Table 43.
Mnemonic
m_pson_r
Description
Allows the microprocessor to read the state of PSON. This allows only one
Register
02h
Bit
6
Read/Write
Read-only
ADM1041 to be configured as the PSON interface to the host system.
m_pson_w
Allow the microprocessor to write to control the PSON function of each ASIC.
12h
1
Write-only
When in microprocessor support mode, the principle configuration for controlling
power-on/power-off will be as follows: One ADM1041 would be configured to be
the interface to the host system through the standard PSON pin. This pin would be
configured not to write through to the PSON debounce block. The microprocessor
would poll the status of this ADM1041 by reading m_pson_r. Debouncing would
be done by the microprocessor. If m_pson_r changed state, the microprocessor
would write the new state to m_pson_w in all ADM1041s on the SMBus. If a fault
were to occur on any output, the SMBAlert interrupt would request microprocessor
attention. If this means turning all ADM1041s off, this would be done by writing a
zero to the m_pson_w bit.
m_acsns_r
Allows the microprocessor to read the state of AC SENSE 1/AC SENSE 2. This allows one
02h
7
Read-only
ADM1041 to be configured as the interface to the host power supply.
m_acsns_w
Allow the microprocessor to write to control the ACSOK function of each ADM1041.
12h
5
Write-only
When in microprocessor support mode the principle configuration for controlling
AC_OK, undervoltage blanking, PEN gating, and RAMP/SS gating will be as follows:
One ADM1041 will be configured to be the interface with the host power supply
AC monitoring circuitry. This ADM1041 might be configured so that the acsns
signal would be written through or would not be written through. Regardless, the
microprocessor would monitor m_acsns_r and write to m_acsns_w as appropriate.
Since it is possible to sense but not to write through, it is possible to configure a
second ADM1041 to monitor a second ac or bulk voltage.
m_shr_clmp
Allow the μP to write directly to m_shr_clmp to control when the ISHARE clamp is
13h
2
Write-only
released. During a hot-swap insertion, there may be a need to delay the release of
the ISHARE clamp. This allows the designer an option over the default release at
75% or 88% of the reference ramp (soft-start).
m_cbd_w
Allow the microprocessor to write directly to CBD as a possible way of adding an
1Bh
1
Write-only
additional output port. This might be for blinking LEDs or as a FAIL signal to the
system.
m_cbd_clr
Allows the microprocessor to clear the CBD latch following an SMBalert. If CBD is
13h
0
Write-only
configured to be latching, there may be circumstances that lead to CBD/SMBAlert
being set by, for example, one of the MON flags but does not lead to PSON being
cycled and CBD being reset. In this case, the microprocessor needs to write directly
to CBD to reset the latch.
mfg5
mfg4
mfg3
mfg2
mfg1
ocpto
uvfault
ovfault
vddov
extrefok
intrefok
gndok
V DD OK
This flag indicates the status of the MON5 pin.
This flag indicates the status of the MON4 pin.
This flag indicates the status of the MON3 pin.
This flag indicates the status of the MON2 pin.
This flag indicates the status of the MON1 pin.
If this flag is high, an overcurrent has occurred and timed out.
If this flag is high, an undervoltage has been sensed
If this flag is high, an overvoltage has been sensed.
If this flag is high, a V DD overvoltage has been sensed.
If this flag is low, the externally available reference on Pin 18 is overloaded.
If this flag is low, the internal reference has no integrity.
If this flag is low, the ASIC ground, Pin 7, is open either pin to PCB or bond wires.
If this flag is low, V DD is below its UVL or the power mangement block has a
00h
00h
00h
00h
00h
00h
00h
00h
01h
01h
01h
01h
01h
0
1
2
3
4
5
6
7
0
1
2
3
4
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
read only
Read-only
Read-only
Read-only
Read-only
problem, a reference voltage, ground fault, or V DD overvoltage fault.
reverseok
orfetok
Share_OK
fault
PULSE_OK
If this flag is low, the OrFET has an excessive reverse voltage.
If this flag is low, either PULSE_OK, penok, loadvok, or reverseok is false.
If this flag is low, the current share accuracy is out of limits.
Fault latch. If this flag is high, either an ovfault, uvfault, or ocp has occured.
Pulses are present at AC SENSE 1.
01h
01h
01h
02h
02h
5
6
7
0
1
Read-only
Read-only
Read-only
Read-only
Read-only
Rev. A | Page 52 of 64
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